Traditionally, logic circuits have been synchronous, and have combined combinatorial logic and sequential logic. Combinatorial logic, such as adders or multiplexers, is used to derive the new state and the outputs of the logic based on inputs to the logic and on the current state of the logic. This current state is obtained from sequential logic, which has output dependent on both its internal state as well as its current inputs. Examples of sequential logic are memory components such as flip-flops (flops) or registers, which contain many flops. The new current state derived by the combinatorial logic is copied to the sequential logic, typically on every rising edge of the clock signal available to the circuit.
Synchronous logic circuits can typically be reset, or cleared, both asynchronously and synchronously. An asynchronous reset is typically activated and cleared externally. When activated, the asynchronous reset immediately resets sequential logic. A synchronous reset is generated internally by combinatorial logic, and resets sequential logic, typically on a subsequent rising clock edge. Since the synchronous reset allows the full clock period for circuit operation, the synchronous reset simplifies circuit design, timing closure, and testing.
FIG. 1 illustrates a logical block diagram of a prior art system 150 with synchronous and asynchronous reset functions. Input data 100 is processed by processing logic 120, typically consisting of combinatorial logic, generating output data 108. The processing logic 120 stores state information in sequential logic 124 via logic input signal 110, and obtains state information from the sequential logic 124 via logic output signal 112. A reset module 140 receives an input control signal 118 from the processing logic 120 and an external input asynchronous reset signal 102. Based on the input control signal 118, synchronous reset initiation logic 122 within the reset module 140, typically consisting of combinatorial logic and sequential logic, determines when to reset the sequential logic 124 via a synchronous reset signal 114. The synchronous reset signal 114 is applied to synchronous reset input 132 of the sequential logic 124. The synchronous reset of the sequential logic 124 is typically on the rising edge of a clock input 106 to the system 150. Based on the input asynchronous reset signal 102, reset logic 126 within the reset module 140 resets the sequential logic 124 and the synchronous reset initiation logic 122 via an asynchronous reset signal 116. The asynchronous reset signal 116 is applied to asynchronous reset input 130 of the sequential logic 124. The sequential logic 124 is therefore typically reset both asynchronously and synchronously, while the reset logic 126 and the synchronous reset initiation logic 122 are typically reset only asynchronously. The reset logic 126 also has a direct current (DC) supply voltage input 104.
FIG. 2 illustrates a schematic of an element of the sequential logic 124 that can be synchronously and asynchronously reset, in accordance with prior art. The synchronous reset signal 114, which is active low, is applied to the synchronous reset input 132 on mux (multiplexer) 204, and controls which of the logic input signal 110 or ground 202 is selected as output 200 of mux 204. Flop 210 sees mux output 200 on its D-pin 212, the clock input 106 on its clock pin 214, and the asynchronous reset signal 116, which is active low, on its C-pin 216. The asynchronous reset signal 116 is applied to the asynchronous reset input 130 of the flop 210. The logic output signal 112 of the sequential logic 124 is on Q-pin 218 of the flop 210. The mux 204 is typically used to enable the synchronous reset of the flop 210 via the D-pin 212, since the flop 210 typically has no pin dedicated for synchronous reset. Additional logic beyond the flop 210, such as the mux 204, is therefore typically required to enable both synchronous and asynchronous reset of the sequential logic 124.
FIG. 3 illustrates a schematic of the reset logic 126 enabling the asynchronous activation and the synchronous release of the asynchronous reset signal 116, in accordance with prior art. The asynchronous reset signal 116 is connected to the asynchronous reset input 130 of the sequential logic 124. Flop 310 sees the DC supply voltage input 104 on its D-pin (data input pin) 312, the clock input 106 on its clock pin 314, and the input asynchronous reset signal 102, which is active low, on its C-pin (clear pin, typically for asynchronous reset) 316. Flop output signal 300 of the flop 310 is on its Q-pin (data output pin) 318. Flop 320 sees the flop output signal 300 of the flop 310 on its D-pin 322, the clock input 106 on its clock pin 324, and the input asynchronous reset signal 102, which is active low, on its C-pin 326. The output of the flop 320 is the asynchronous reset signal 116.
Though asynchronous activation of asynchronous reset is essentially immediate, it is important for the release of asynchronous reset to be synchronous, typically on a rising clock edge. The reset logic 126 shown in FIG. 3 guarantees that, upon the clearing of the input asynchronous reset signal 102, the asynchronous reset signal 116 does not clear (corresponding to passing the DC supply voltage 104 through the flop 310 and the flop 320) until the second subsequent rising edge of the clock input 106. This typically provides sufficient time for the logic in the system 150 to clear. If more time is required, additional flop states can be added to the reset logic 126.
Logic synthesis, which converts a register-transfer level (RTL) description of digital logic into a gate-level description, results in additional gates, such as multiplexers, in sequential logic elements when synchronous reset is added to circuits providing asynchronous reset. In a wireless local area network (LAN) transceiver, a large number of sequential logic elements is typically simultaneously reset upon completion of processing of an input data packet, since there is no need to maintain state information for processing of the subsequent data packet. Therefore, any gate savings obtainable across every sequential logic element can be significant in terms of area, power, and cost savings. These savings can also aid in timing closure. It would be highly desirable to provide a method, apparatus, and system for synchronously resetting logic circuits that reduces the number of additional gates for applications with many sequential logic elements, in particular by reducing the number of gates required to enable both synchronous and asynchronous reset of sequential logic.